효율적인 Partial Scan 설계 알고리듬

• Published in: 전기학회 논문지 P권, 53(4) Vol. 53P; no. 4; pp. 210 - 215
• Main Authors: 金倫弘(Yun-Hong Kim), 新載興(Jae-Heung Shin)
• Format: Journal Article
• Language: Korean
• Published: 대한전기학회 2004
• Subjects: 전기공학; Sequential circuit; Partial scan; Feedback vertex set; Logic synthesis
• ISSN: 1229-800X; 2586-7792

This paper proposes an implicit method for computing the minimum cost feedback vertex set for a graph. For an arbitrary graph, a Boolean function is derived, whose satisfying assignments directly correspond to feedback vertex sets of the graph. Importantly, cycles in the graph are never explicitly enumerated, but rather, are captured implicitly in this Boolean function. This function is then used to determine the minimum cost feedback vertex set. Even though computing the minimum cost satisfying assignment for a Boolean function remains an NP-hard problem, it is possible to exploit the advances made in the area of Boolean function representation in logic synthesis to tackle this problem efficiently in practice for even reasonably large sized graphs. The algorithm has obvious application in flip-flop selection for partial scan. The algorithm proposed in this paper is the first to obtain the MFVS solutions for many benchmark circuits.