A Low-Spur CMOS PLL Using Differential Compensation Scheme

• Published in: ETRI journal Vol. 34; no. 4; pp. 518 - 526
• Main Authors: Yun, Seok-Ju, Kim, Kwi-Dong, Kwon, Jong-Kee
• Format: Journal Article
• Language: Korean
• Published: 한국전자통신연구원 31.08.2012; ETRI
• Subjects: CMOS; spur rejection; integrated circuit design; transformer; differentially-tuned; Phase-locked loop (PLL); voltage-controlled oscillator (VCO)
• ISSN: 1225-6463; 2233-7326

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.