Low-clock-speed time-interleaved architecture for a polar delta–sigma modulator transmitter

The polar delta-sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software-defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitter architecture. This study proposes a low-complexit...

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Bibliographic Details
Published inETRI journal Vol. 45; no. 1; pp. 150 - 162
Main Authors Nasser Erfani Majd, Rezvan Fani
Format Journal Article
LanguageKorean
Published 한국전자통신연구원 28.02.2023
ETRI
Subjects
oversampling ratio
software-defined radio
delta-sigma modulator
signal-to-noise-anddistortion ratio
long-term evolution
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Summary:The polar delta-sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software-defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitter architecture. This study proposes a low-complexity timeinterleaved architecture for the polar DSM transmitter baseband part to reduce the clock speed requirement of the polar DSM transmitter using an upsampling technique. Simulations show that using the proposed four-branch timeinterleaved polar DSM transmitter baseband part, the clock speed requirement of the transmitter is reduced by four times without degrading the signal-tonoise-and-distortion ratio.
Bibliography:KISTI1.1003/JNL.JAKO202355350318397
ISSN:1225-6463
2233-7326