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As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error dete...

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Bibliographic Details
Published in한국정보통신학회논문지 Vol. 26; no. 11; pp. 1747 - 1750
Main Author 전호윤(Hoyoon Jun)
Format Journal Article
LanguageKorean
Published 한국정보통신학회 2022
Subjects
Error Correction Code
On-chip Memory
soft errors
multiple bit upset
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ISSN2234-4772
2288-4165

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Summary:As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.
Bibliography:KISTI1.1003/JNL.JAKO202203255691370
ISSN:2234-4772
2288-4165