Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix...

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Bibliographic Details
Published inETRI journal Vol. 32; no. 2; pp. 222 - 229
Main Authors Hwang, Soo-Yun, Park, Gi-Yoon, Kim, Dae-Ho, Jhang, Kyoung-Son
Format Journal Article
LanguageKorean
Published 한국전자통신연구원 30.04.2010
ETRI
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Summary:A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a $2{\times}2$ multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.
Bibliography:KISTI1.1003/JNL.JAKO201071242949050
ISSN:1225-6463
2233-7326