Design and Implementation of Unified Hardware for 128-Bit Block Ciphers ARIA and AES

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures...

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Bibliographic Details
Published inETRI journal Vol. 29; no. 6; pp. 820 - 822
Main Authors Koo, Bon-Seok, Ryu, Gwon-Ho, Chang, Tae-Joo, Lee, Sang-Jin
Format Journal Article
LanguageKorean
Published 한국전자통신연구원 06.02.2007
ETRI
Subjects
hardware architecture
resource sharing
ARIA
AES
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Summary:ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.
Bibliography:KISTI1.1003/JNL.JAKO200771242946848
ISSN:1225-6463
2233-7326