High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs

• Published in: ETRI journal Vol. 30; no. 5; pp. 707 - 717
• Main Authors: Lee, Sang-Woo, Moon, Sang-Jae, Kim, Jeong-Nyeo
• Format: Journal Article
• Language: Korean
• Published: 한국전자통신연구원 05.02.2008; ETRI
• Subjects: cryptography; block cipher; hardware architecture; ARIA
• ISSN: 1225-6463; 2233-7326

This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area-throughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for non-feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over $GF(2^4)^2$, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 ${\mu}m$ CMOS technology. This is the first sub-pipelined architecture of ARIA for high throughput to date.