A 10-bit Current-steering DAC in 0.35-μm CMOS Process

• Published in: Transactions on electrical and electronic materials Vol. 10; no. 2; pp. 44 - 48
• Main Authors: Cui, Zhi-Yuan, Piao, Hua-Lan, Kim, Nam-Soo
• Format: Journal Article
• Language: Korean
• Published: 한국전기전자재료학회 25.04.2009
• Subjects: CMOS symmetrical switching; Current-steering; DAC; High-speed; Segmented architecture; High-speed; Segmented architecture; Current-steering; DAC; CMOS symmetrical switching
• ISSN: 1229-7607; 2092-7592

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.