Improved Test Pattern Generation for Hardware Trojan Detection Using Genetic Algorithm and Boolean Satisfiability

• Published in: Cryptographic Hardware and Embedded Systems -- CHES 2015 Vol. 9293; pp. 577 - 596
• Main Authors: Saha, Sayandeep, Chakraborty, Rajat Subhra, Nuthakki, Srinivasa Shashank, Anshul, Mukhopadhyay, Debdeep
• Format: Book Chapter
• Language: English
• Published: Germany Springer Berlin / Heidelberg 2015; Springer Berlin Heidelberg
• Series: Lecture Notes in Computer Science
• Subjects: Benchmark Circuit; Conjunctive Normal Form; Data encryption; Fault List; Information architecture; Network hardware; Test Vector; Trigger Condition
• ISBN: 3662483238; 9783662483237
• ISSN: 0302-9743; 1611-3349
• DOI: 10.1007/978-3-662-48324-4_29

Test generation for Hardware Trojan Horses (HTH) detection is extremely challenging, as Trojans are designed to be triggered by very rare logic conditions at internal nodes of the circuit. In this paper, we propose a Genetic Algorithm (GA) based Automatic Test Pattern Generation (ATPG) technique, enhanced by automated solution to an associated Boolean Satisfiability problem. The main insight is that given a specific internal trigger condition, it is not possible to attack an arbitrary node (payload) of the circuit, as the effect of the induced logic malfunction by the HTH might not get propagated to the output. Based on this observation, a fault simulation based framework has been proposed, which enumerates the feasible payload nodes for a specific triggering condition. Subsequently, a compact set of test vectors is selected based on their ability to detect the logic malfunction at the feasible payload nodes, thus increasing their effectiveness. Test vectors generated by the proposed scheme were found to achieve higher detection coverage over large population of HTH in ISCAS benchmark circuits, compared to a previously proposed logic testing based Trojan detection technique.