HIGH-QUALITY SiO2/Si INTERFACE FORMATION AND ITS APPLICATION TO FABRICATION OF LOW-TEMPERATURE-PROCESSED POLYCRYSTALLINE Si THIN-FILM TRANSISTOR

• Published in: Jpn.J.Appl.Phys ,Part 1. Vol. 41, no. 6A, pp. 3646-3650. 2002 Vol. 41; no. 6A; pp. 3646 - 3650
• Main Authors: Higashi, S, Abe, D, Hiroshima, Y, Miyashita, K, Kawamura, T, Inoue, S
• Format: Journal Article
• Language: English
• Published: 2002
• ISSN: 0021-4922
• DOI: 10.1143/jjap.41.3646

Improvement of SiO2/Si interface quality and its effect on the performance of low-temperature-processed polycrystalline Si thin-film transistors (poly-Si TFTs) are investigated. Two gate SiO2 formation conditions for realizing the density of interface states (Dit) at mid-gap of 1.4 x 1011 and 4.1 x 1010 cm-2eV-1 were applied to a 425 C TFT fabrication process using ECR PECVD. By reducing Dit, reduction of threshold voltage from 1.97 to 1.12 V, reduction of sub-threshold swing from 303 to 250 mV/decade and increase of mobility from 196 to 309 cm2V-1s-1 were observed. The analysis of TFT characteristics indicated the decrease of both deep and shallow level trap states. Not only threshold voltage and sub-threshold swing but also the mobility of the poly-Si TFT were improved. Results indicate that low-temperature process technologies for forming a high-quality SiO2/Si interface are important for next-generation high-performance poly-Si TFTs. 26 refs.