Power-Aware Dynamic Cache Partitioning for CMPs

• Published in: Transactions on High-Performance Embedded Architectures and Compilers III pp. 135 - 153
• Main Authors: Kotera, Isao, Abe, Kenta, Egawa, Ryusuke, Takizawa, Hiroyuki, Kobayashi, Hiroaki
• Format: Book Chapter
• Language: English; Japanese
• Published: Berlin, Heidelberg Springer Berlin Heidelberg 2011
• Series: Lecture Notes in Computer Science
• Subjects: Cache Access; Hardware Overhead; Shared Cache; Static Power Consumption; Very Large Scale Integration
• ISBN: 3642194478; 9783642194474
• ISSN: 0302-9743; 1611-3349
• DOI: 10.1007/978-3-642-19448-1_8

Cache partitioning and power-gating schemes are major research topics to achieve a high-performance and low-power shared cache for next generation chip multiprocessors(CMPs). We propose a poweraware cache partitioning mechanism, which is a scheme to realize both low power and high performance using power-gating and cache partitioning at the same time. The proposed cache mechanism is composed of a way-allocation function and power control function; each function works based on the cache locality assessment. The performance evaluation results show that the proposed cache mechanism with a performanceoriented parameter setting can reduce energy consumption by 20% while keeping the performance, and the mechanism with an energy-oriented parameter setting can reduce 54% energy consumption with a performance degradation of 13%. The hardware implementation results indicate that the delay and area overheads to control the proposed mechanism are negligible, and therefore hardly affect both the entire chip design and performance.