A Waiting Mechanism with Conflict Prediction on Hardware Transactional Memory

Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilites, and Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed...

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Bibliographic Details
Published inIEICE transactions on information and systems Vol. E99.D; no. 12; pp. 2860 - 2870
Main Authors Mashita, Keisuke, Tabuchi, Maya, Yamada, Ryohei, Tsumura, Tomoaki
Format Journal Article
LanguageJapanese
Published 2016
Subjects
Encounters
Hardware
Locks
Microprocessors
Parallel programming
Processors
Synchronism
Synchronization
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Summary:Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilites, and Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed speculatively in parallel as long as they do not encounter any conflicts on shared variables. On general HTMs: hardware implementations of TM, transactions which have conflicted once each other will conflict repeatedly if they will be executed again in parallel, and the performance of HTM will decline. To address this problem, in this paper, we propose a conflict prediction to avoid conflicts before executing transactions, considering historical data of conflicts. The result of the experiment shows that the execution time of HTM is reduced 59.2% at a maximum, and 16.8% on average with 16 threads.
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ISSN:0916-8532
1745-1361
DOI:10.1587/transinf.2016PAP0006