Artificial Bee Colony Optimization to Accelerate High-Speed Serial I/O Tx Equalization

A critical activity during electrical testing for High-Speed Serial l/O is the search for optimal Tx equalization settings that yield the cleanest eye diagram possible. Typical practices consist of performing an exhaustive grid search over two variables to define the best solution region, known as t...

Full description

Saved in:
Bibliographic Details
Published inProceedings - IEEE VLSI Test Symposium pp. 1 - 5
Main Authors Sanchez-Martinez, Cesar A., Lopez-Meyer, Paulo, Viveros-Wacher, Andres
Format Conference Proceeding
LanguageEnglish
Published IEEE 28.04.2025
Subjects
Approximation algorithms
artificial bee colony
Artificial bee colony algorithm
Eye Margins
Heuristic algorithms
HSIO
Optimization
Proposals
Space exploration
Technological innovation
Testing
Tx Equalization
Very large scale integration
Visualization
Online AccessGet full text

Cover

More Information
Summary:A critical activity during electrical testing for High-Speed Serial l/O is the search for optimal Tx equalization settings that yield the cleanest eye diagram possible. Typical practices consist of performing an exhaustive grid search over two variables to define the best solution region, known as the pre-cursor and the post-cursor. This work introduces a methodology to obtain a precise approximation to the optimal equalization values based on the artificial bee colony (ABC) heuristic optimization algorithm. This algorithm explores the solution space with fewer combinations than the typically used procedure. In this work we demonstrate experimentally that the ABC algorithm converges to the solution region of the equalization settings in 36% of the time needed by a grid search. The algorithm was tested on PCIe Gen 5, but lower speed PCIe generations and other interfaces subject to Tx equalization could benefit from these optimization tools, e.g. CXL, UPI, DMI, etc.
ISSN:2375-1053
DOI:10.1109/VTS65138.2025.11022872