Special Session: Security Verification of Microelectronic Systems with Integrated AI Accelerators: Scope, Practice, and Challenges

The rapid advancement of artificial intelligence (AI) has resulted in creation of a vast array of accelerator hardware, including GPUs, TPUs, and FPGAs, alongside the latest ASICs, to efficiently train and deploy AI models. However, AI accelerators are vulnerable to security threats that can comprom...

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Bibliographic Details
Published inProceedings - IEEE VLSI Test Symposium pp. 1 - 4
Main Authors Islam, Kazi Mejbaul, Tabassum, Tambiara, Halder, Dipal, Ray, Sandip
Format Conference Proceeding
LanguageEnglish
Published IEEE 28.04.2025
Subjects
AI accelerators
Field programmable gate arrays
Hardware
Microelectronics
Security
Verification
Very large scale integration
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Summary:The rapid advancement of artificial intelligence (AI) has resulted in creation of a vast array of accelerator hardware, including GPUs, TPUs, and FPGAs, alongside the latest ASICs, to efficiently train and deploy AI models. However, AI accelerators are vulnerable to security threats that can compromise sensitive information, such as model architecture and jeopardize operational integrity, leading to unreliable applications. While significant efforts have been made for security verification of AI accelerators, existing techniques have inherent limitations and struggle to keep pace with evolving attack strategies. In this paper, we present a comprehensive analysis of the evolving field of security verification methodologies for AI accelerators, critically examining their effectiveness and identifying key limitations. Furthermore, we explore emerging trends in the field and outline potential research directions that could be pursued to enhance the security verification of AI accelerators.
ISSN:2375-1053
DOI:10.1109/VTS65138.2025.11022911