Design and Implementation of FIR Filter Using Different Architectures: A Comparative Study

• Published in: International Conference on Signal Processing and Communication (Online) pp. 659 - 664
• Main Authors: Soni, Teena, Kumar, Anil, Panda, Manoj Kumar
• Format: Conference Proceeding
• Language: English
• Published: IEEE 20.02.2025
• Subjects: Arithmetic; ASIC; Attenuation; Costs; Field programmable gate arrays; Finite impulse response filters; FIR Filter; FPGA; Implementation; Optimization; Particle swarm optimization; Passband; Signal processing algorithms; Throughput
• ISSN: 2643-444X
• DOI: 10.1109/ICSC64553.2025.10968271

The article proposes a hybrid sparse particle swarm optimization algorithm (HSPSO). This paper also presents an improved low-pass FIR filter design utilizing the HSPSO algorithm. The effectiveness of the proposed algorithm is contrasted with particle swarm optimization and sparse PSO in resolving the FIR filter design problem. HSPSO offered smaller best cost and execution time values. Furthermore, the suggested approach competes with the existing approaches in the literature, providing higher stopband attenuation values and smaller passband ripple values. The proposed work implemented the designed FIR filters, employing various multiplierless techniques, including the canonical signed digit (CSD) number system, fractional CSD (FCSD), distributed arithmetic (DA), and parallel distributed arithmetic (PDA). The comparative study of all the architectures and multiplier-based structure (MULT) is performed for the FPGA and ASIC environments. The DA outperforms all the architecture in area and power. The PDA with decomposition factor 4 provides the highest throughput and also smaller area and power compared with MULT, CSD, and FCSD-based architecture.