Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance

• Published in: Proceedings - International Symposium on High-Performance Computer Architecture pp. 849 - 866
• Main Authors: Olgun, Ataberk, Bostanci, F. Nisa, Yuksel, Ismail Emir, Canpolat, Oguzhan, Luo, Haocong, Oliveira, Geraldo F., Yaglikci, A. Giray, Patel, Minesh, Mutlu, Onur
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2025
• Subjects: DRAM chips; Error correction codes; Prevention and mitigation; Reliability; Security; Semiconductor device measurement; Size measurement; Temperature distribution; Temperature measurement; Time measurement
• ISSN: 2378-203X
• DOI: 10.1109/HPCA61900.2025.00069

Modern DRAM chips are subject to read disturbance errors. These errors manifest as security-critical bitflips in a victim DRAM row that is physically nearby a repeatedly activated (opened) aggressor row (RowHammer) or an aggressor row that is kept open for a long time (RowPress). State-of-the-art read disturbance mitigations rely on accurate and exhaustive characterization of the read disturbance threshold (R D T) (e.g., the number of aggressor row activations needed to induce the first RowHammer or RowPress bitflip) of every DRAM row (of which there are millions or billions in a modern system) to prevent read disturbance bitflips securely and with low overhead. We experimentally demonstrate for the first time that the RDT of a DRAM row significantly and unpredictably changes over time. We call this new phenomenon variable read disturbance (VRD). Our extensive experiments using 160 DDR4 chips and 4 HBM2 chips from three major manufacturers yield three key observations. First, it is very unlikely that relatively few RDT measurements can accurately identify the RDT of a DRAM row. The minimum RDT of a DRAM row appears after tens of thousands of measurements (e.g., up to 94,467), and the minimum RDT of a DRAM row is 3.5 \times smaller than the maximum RDT observed for that row. Second, the probability of accurately identifying a row's RDT with a relatively small number of measurements reduces with increasing chip density or smaller technology node size. Third, data pattern, the amount of time an aggressor row is kept open, and temperature can affect the probability of accurately identifying a DRAM row's RDT. Our empirical results have implications for the security guarantees of read disturbance mitigation techniques: if the RDT of a DRAM row is not identified accurately, these techniques can easily become insecure. We discuss and evaluate using a guardband for RDT and error-correcting codes for mitigating read disturbance bitflips in the presence of RDTs that change unpredictably over time. We conclude that a\gt 10 \% guardband for the minimum observed RDT combined with SECDED or Chipkill-like SSC error-correcting codes could prevent read disturbance bitflips at the cost of large read disturbance mitigation performance overheads (e.g., 45% performance loss for an RDT guardband of 50 \%). We hope and believe future work on efficient online profiling mechanisms and configurable read disturbance mitigation techniques could remedy the challenges imposed on today's read disturbance mitigations by the variable read disturbance phenomenon.