Optimized Channel Length and Off State Current for InAs/Si Heterojunction TFET

this paper contains the Optimization and Comparative study of the Planar Architecture of InAs/Si Heterojunction TFETs. Optimizations performed on the Original Model such as Channel length is reduced to 45nm and Gate Metal overlapping is introduced. Doping concentrations are varied to optimize the el...

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Bibliographic Details
Published inInternational Conference on Signal Processing and Communication (Online) pp. 862 - 867
Main Authors Sachan, Mayank, Devi, Wangkheirakpam Vandana, Bharti, Manisha
Format Conference Proceeding
LanguageEnglish
Published IEEE 20.02.2025
Subjects
Heterojunctions
Indium
Indium Arsenide / Silicon Heterojunction TFET
Ions
Logic gates
Off state Current On state Current Sub-threshold Swing Gate Metal Overlapping
Optimization
Performance evaluation
Planar Architecture
Semiconductor process modeling
Signal processing
Silicon
TFETs
Tunnel Field Effect Transistors (TFET)
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ISSN2643-444X
DOI10.1109/ICSC64553.2025.10968585

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Summary:this paper contains the Optimization and Comparative study of the Planar Architecture of InAs/Si Heterojunction TFETs. Optimizations performed on the Original Model such as Channel length is reduced to 45nm and Gate Metal overlapping is introduced. Doping concentrations are varied to optimize the electrical device parameter after modifying the physical dimensions of the original model. The Optimized model presented shows some significant improvements such as Reduced off state current (I off ) while on state current (Ion) remains same and minimum Subthreshold swing slightly increased to 7.3mV/Dec. I on by I off ratio is about 10 10 . Comparative study with Original Model and other parameters of the optimized model are presented further in the paper.
ISSN:2643-444X
DOI:10.1109/ICSC64553.2025.10968585