Analysis of Sub-Sampling PLL False Lock and Lock-in Range Estimation

The Sub-sampling PLL (SSPLL) has attracted significant interest from researchers due to its low phase error and high operating frequency. However, the sub-sampling phase detector (SSPD) is sensitive only to phase error, not frequency error, which may cause false locking into undesired frequencies. T...

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Bibliographic Details
Published inIEEE International Symposium on Circuits and Systems proceedings pp. 1 - 5
Main Authors Chen, Wenzhe, Xia, Tian
Format Conference Proceeding
LanguageEnglish
Published IEEE 25.05.2025
Subjects
Circuits and systems
Detectors
Estimation
false-lock
Frequency estimation
Integrated circuit modeling
lock-in range
Performance evaluation
Phase frequency detectors
Phase locked loops
Stability analysis
State-space methods
state-space model
sub-sampling
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ISSN2158-1525
DOI10.1109/ISCAS56072.2025.11043672

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Summary:The Sub-sampling PLL (SSPLL) has attracted significant interest from researchers due to its low phase error and high operating frequency. However, the sub-sampling phase detector (SSPD) is sensitive only to phase error, not frequency error, which may cause false locking into undesired frequencies. This paper provides a detailed analysis of the sub-sampling process and discusses false locking scenarios. Furthermore, the lock-in range, which is the boundary between the system's linear and non-linear behavior, is also investigated. It is a key characteristic of system stability and a constraint in the design of auxiliary devices. This paper develops a state-space model that considers the sinusoidal characteristics of the SSPD to analyze frequency acquisition behavior and estimate the lock-in range.
ISSN:2158-1525
DOI:10.1109/ISCAS56072.2025.11043672