ChipMnd: LLMs for Agile Chip Design

• Published in: Proceedings - IEEE VLSI Test Symposium pp. 1 - 10
• Main Authors: Firouzi, Farshad, Pan, David Z., Gu, Jiaqi, Farahani, Bahar, Chaudhuri, Jayeeta, Yin, Ziang, Ma, Pingchuan, Domanski, Peter, Chakrabarty, Krishnendu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 28.04.2025
• Subjects: AI for chip design; Chip scale packaging; Complexity theory; Design automation; Design methodology; Electronic Design Automation (EDA); Hardware security; Large language models; Large Language Models (LLMs); Optimization; Scalability; Test pattern generators; Very large scale integration
• ISSN: 2375-1053
• DOI: 10.1109/VTS65138.2025.11022936

The increasing complexity of semiconductor design, along with stringent performance, power, and time-to-market requirements, has outpaced the capabilities of traditional Electronic Design Automation (EDA) methodologies. Conventional design workflows rely on manual intervention for critical tasks suc...