ChipMnd: LLMs for Agile Chip Design

• Published in: Proceedings - IEEE VLSI Test Symposium pp. 1 - 10
• Main Authors: Firouzi, Farshad, Pan, David Z., Gu, Jiaqi, Farahani, Bahar, Chaudhuri, Jayeeta, Yin, Ziang, Ma, Pingchuan, Domanski, Peter, Chakrabarty, Krishnendu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 28.04.2025
• Subjects: AI for chip design; Chip scale packaging; Complexity theory; Design automation; Design methodology; Electronic Design Automation (EDA); Hardware security; Large language models; Large Language Models (LLMs); Optimization; Scalability; Test pattern generators; Very large scale integration
• ISSN: 2375-1053
• DOI: 10.1109/VTS65138.2025.11022936

The increasing complexity of semiconductor design, along with stringent performance, power, and time-to-market requirements, has outpaced the capabilities of traditional Electronic Design Automation (EDA) methodologies. Conventional design workflows rely on manual intervention for critical tasks such as hardware description, synthesis optimization, and verification, leading to inefficiencies and scalability limitations. Large Language Models (LLMs) present a transformative approach by automating key stages of the design pipeline, enabling intelligent synthesis tuning, test generation, and security analysis. This paper introduces ChipMind, an LLM-driven framework comprising specialized agents and modules for digital and analog chip design. ChipMind integrates AI-driven methodologies to enhance design efficiency, accelerate prototyping, and optimize key design trade-offs, thereby addressing fundamental challenges in modern semiconductor development.