Defects, Fault Modeling, and Test Development Framework for FeFETs

• Published in: Proceedings - International Test Conference pp. 91 - 95
• Main Authors: Wang, Changhao, Yuan, Sicong, Xun, Hanzhi, Li, Chaobo, Taouil, Mottaqiallah, Fieback, Moritz, Chen, Danyang, Li, Xiuyan, Wang, Lin, Cantoro, Riccardo, Yin, Chujun, Hamdioui, Said
• Format: Conference Proceeding
• Language: English
• Published: IEEE 03.11.2024
• Subjects: Analytical models; defect modeling; device-aware defect model; fault modeling; fefet; FeFETs; Manufacturing; memory test; Nonvolatile memory; Transistors
• ISSN: 2378-2250
• DOI: 10.1109/ITC51657.2024.00026

As emerging non-volatile memory (NVM) devices, Ferroelectric Field-Effect Transistors (FeFETs) present distinctive opportunities for the design of ultra-dense and low-leakage memory systems. For matured FeFET manufacturing, it is extremely important to have an understanding of manufacturing defects and accurately model them to develop effective test solutions. This paper introduces a comprehensive framework for defect and fault modeling, which enables the development of test solutions. First, a classification of FeFET manufacturing defects is provided; both conventional defects (such as contacts and interconnect defects) as well as unique FeFET defects are discussed. The latter FeFET specific defect leads to unique faults that cannot be adequately described using traditional modeling approaches. Then, the Device-Aware Test (DAT) method is used to effectively and appropriately model, analyze and develop test solutions for such unique defects; the approach will be illustrated for Stuck-at-Polarization (SAP) defects.