PESA: Power-Efficient SPHINCS+ Accelerator for Multi-Domain Security Applications on FPGA SoC

• Published in: International Symposium on Computing and Networking (Online) pp. 231 - 237
• Main Authors: Le, Vu Trung Duong, Pham, Anh Kiet, Pham, Hoai Luan, Vu, Tuan Hai, Nakashima, Yasuhiko
• Format: Conference Proceeding
• Language: English
• Published: IEEE 26.11.2024
• Subjects: Computational efficiency; Cryptography; Field programmable gate arrays; FPGA; Hash functions; Optimization; Organizations; Post-Quantum Cryptography; Power demand; power efficiency; Protection; Real-time systems; SoC; Software; SPHINCS
• ISSN: 2379-1896
• DOI: 10.1109/CANDAR64496.2024.00037

The continuous growth of large-scale computing systems requires the development of a high-speed, low-power hardware platform for post-quantum cryptography (PQC) to meet strict security and information protection requirements. However, recent studies on PQC software and hardware accelerators continue to face challenges with low performance and high power consumption. Therefore, this paper proposes a power-efficient SPHINCS+ accelerator, called PESA, to achieve high processing speed and power efficiency for SPHINCS+-SHA-256 computations. In particular, PESA applies three key optimizations: memory organization for high-bandwidth transmission, a high-speed SHA-256 quad-core for WOTS+ acceleration, and a resource-sharing SHA-256 technique. Evaluation results on the Xilinx ZCU102 FPGA demonstrate that PESA achieves signing speeds 4.34 to 286 times faster than existing FPGA-based implementations. Compared to the conventional design, PESA reduces signing latency by 71.2%, improves signing speed by 2.97 to 3.48 times, and achieves a better power delay product (PDP) by 3.66 to 4.79 times. Notably, comparisons in real-time experiments reveal PESA's outstanding performance against powerful CPUs, achieving speeds 1.22 to 4.19 times faster and significantly improving power efficiency, with a PDP improvement of 10.01 to 22.33 times.