Hardware assisted thread assignment for RISC based MPSoCs in invasive computing

One of the major challenges of future many-core architectures is the efficient utilization of the abundance of computing power. Invasive computing provides a computing paradigm wherein applications can economically use the available compute resources. Applications can expand and shrink on demand dep...

Full description

Saved in:
Bibliographic Details
Published in2011 International Symposium on Integrated Circuits pp. 106 - 109
Main Authors Pujari, R. K., Wild, T., Herkersdorf, A., Vogel, B., Henkel, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2011
Subjects
Computer architecture
Hardware
Instruction sets
invasive computing
Monitoring
multiprocessor system on a chip
resource aware programming
Temperature measurement
Temperature sensors
thread assignment
Tiles
Online AccessGet full text

Cover

More Information
Summary:One of the major challenges of future many-core architectures is the efficient utilization of the abundance of computing power. Invasive computing provides a computing paradigm wherein applications can economically use the available compute resources. Applications can expand and shrink on demand depending on their thread level parallelism and resource availability. In this paper we present an analytical justification for performing a hardware-software co-optimization of the thread assignment in a resource aware programming environment. We propose a dedicated hardware block to support thread assignments as an architectural extension to standard MPSoC designs.
ISBN:161284863X
9781612848631
ISSN:2325-0631
DOI:10.1109/ISICir.2011.6131920