A 342mW mobile application processor with full-HD multi-standard video codec

• Published in: 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers pp. 158 - 159,159a
• Main Authors: Iwata, K., Irita, T., Mochizuki, S., Ueda, H., Ehama, M., Kimura, M., Takemura, J., Matsumoto, K., Yamamoto, E., Teranuma, T., Takakubo, K., Watanabe, H., Yoshioka, S., Hattori, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2009
• Subjects: Bandwidth; Cellular phones; Circuits; Decoding; Energy consumption; High definition video; Intellectual property; Multicore processing; Video codecs; Visualization
• ISBN: 9781424434589; 1424434580
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2009.4977356

Today's cellular phones must support full high-definition (full-HD) video in multiple video formats, such as H.264 and MPEG-2/-4, with low power consumption. Full-HD video processing requires six times the data bandwidth and is more computationally intensive than conventional standard-definition (SD) video. The trade-off between flexibility, performance and power consumption is a key focus of video-codec design. Homogeneous multi-core processors are power-consuming and achieving high-throughput is difficult. While dedicated circuits can minimize power consumption, the dedicated decoders and encoders in previous reports have difficulty performing all of the media processing that is indispensable for a modern cellular phone. In this paper, we have integrated a mobile application processor featuring a two-stage-processing video codec, tile-based address-translation circuits, and several audio/visual intellectual property (IP) modules. The circuit diagram and visualization are also illustrated.