Ground plane SOI MOSFET based SRAM with consideration of process variation

• Published in: 2010 IEEE International Conference of Electron Devices and Solid-State Circuits pp. 1 - 4
• Main Authors: Saremi, M, Ebrahimi, B, Afzali-Kusha, Ali
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2010
• Subjects: CMOS integrated circuits; ground plane (GP); Logic gates; MOSFET circuits; Nanoscale devices; Noise; process variations; Random access memory; Silicon-on-insulator (SOI) MOSFET; static random access memory (SRAM) cell; Threshold voltage

In this paper, the characteristics of static random access memory (SRAM) cells based on three silicon-on-insulator (SOI) device structures are studied using device simulations. The comparative study, which is performed in a 32nm standard CMOS technology, includes read static noise margin (read SNM),...