Ground plane SOI MOSFET based SRAM with consideration of process variation

In this paper, the characteristics of static random access memory (SRAM) cells based on three silicon-on-insulator (SOI) device structures are studied using device simulations. The comparative study, which is performed in a 32nm standard CMOS technology, includes read static noise margin (read SNM),...

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Bibliographic Details
Published in2010 IEEE International Conference of Electron Devices and Solid-State Circuits pp. 1 - 4
Main Authors Saremi, M, Ebrahimi, B, Afzali-Kusha, Ali
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2010
Subjects
CMOS integrated circuits
ground plane (GP)
Logic gates
MOSFET circuits
Nanoscale devices
Noise
process variations
Random access memory
Silicon-on-insulator (SOI) MOSFET
static random access memory (SRAM) cell
Threshold voltage
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Summary:In this paper, the characteristics of static random access memory (SRAM) cells based on three silicon-on-insulator (SOI) device structures are studied using device simulations. The comparative study, which is performed in a 32nm standard CMOS technology, includes read static noise margin (read SNM), read current, and standby power. The structures include SOI with ground plane in substrate (SOI-GPS), SOI with ground plane in buried oxide (SOI-GPB), and SOI without ground plane (SOI-WGP). In addition, the variations of the SRAM characteristics due to channel length and thin-film thickness variations are investigated. The results show that the SOI-GPS structure is more resistant against the process variations when compared to the other two structures.
ISBN:9781424499977
1424499976
DOI:10.1109/EDSSC.2010.5713733