A low-complexity, hardware architecture for a parametric, real-time, LSF speech decoder

• Published in: 2011 IEEE 15th International Symposium on Consumer Electronics (ISCE) pp. 488 - 491
• Main Authors: Mabrouk, A., Hassim, N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2011
• Subjects: Computer architecture; Decoding; Hardware; Polynomials; Real time systems; Speech; Speech coding
• ISBN: 1612848435; 9781612848433
• ISSN: 0747-668X; 2159-1423
• DOI: 10.1109/ISCE.2011.5973878

One of the main objectives of the widely used MPEG4 audio standard was to provide a technical framework for audio coding suited for low bit rate wireless communication. All variants of the MPEG4 audio coders use a Linear Prediction (LP) filtering system. The LP filter coefficients are calculated based on the Line Spectral Frequencies (LSF) parameters due to their excellent quantization characteristics. This work presents a hardware architecture that implements the conversion of the LSF parameters into the LP coefficients and the LP synthesis filter. The LSF conversion module is based on a simplified algorithm that cuts down on many arithmetic operations and thus results in a low gate count module. The architecture was implemented on Xilinx Virtex5 FPGA platform for performance measurement and verification. Module speeds are reported in terms of the number of clock cycles taken by each of their sub-modules to show suitability for real-time applications. Synthesis results are reported using various degrees of parallelism to explore the trade-off between gate count and time delay. Fixed-point implementation was carried out in a way that kept the original precision of the LSF parameters and input data in order to mitigate the severe impact of the tight bit rate budget.