Investigation of warpage induced reliability of a system in package in assembly process

The power system in package (SIP) includes multiple chips such as power IGBT, diodes and IC controllers. With more chips encapsulated in one single package, the silicon die crack failure is becoming more and more challenging. In this paper, a leadframe based power SIP package is investigated. The wa...

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Bibliographic Details
Published in2014 15th International Conference on Electronic Packaging Technology pp. 718 - 723
Main Authors Qiuxiao Qian, Yong Liu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2014
Subjects
aseembly
Ceramics
clamping
Clamps
FEA
Finite element analysis
Insulated gate bipolar transistors
Lead
lead frame
Silicon
System in package (SIP)
Tensile stress
warpage
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Summary:The power system in package (SIP) includes multiple chips such as power IGBT, diodes and IC controllers. With more chips encapsulated in one single package, the silicon die crack failure is becoming more and more challenging. In this paper, a leadframe based power SIP package is investigated. The warpage induced reliability in assembly process is studied. The initial leadframe pad warpage will induce high tensile stress in silicon die during clamping process. A 3D FEA model for the assembly clamping process is developed. Parametric modeling DoE is carried out to simulate the impact of different leadframe warpage shape (concave and convex), different lead frame pad warpages, different die sizes, different leadframe thickness and different BLTs.
DOI:10.1109/ICEPT.2014.6922752