Improved Gate Delay Propagation in Static Timing Analysis

This paper presents a methodology to accurately evaluate the input waveforms of CMOS gates for static timing analysis (STA) in the presence of crosstalk noise. Currently, gate delay is calculated by looking-up 2-dimension table using input waveform slope and gate load capacitance, and CMOS gate inpu...

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Bibliographic Details
Published in2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis pp. 1 - 4
Main Authors Zhang, Xuliang, Bao, Jingfu, Sun, Guoying
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2009
Subjects
Analytical models
Capacitance
Crosstalk
Delay effects
Integrated circuit interconnections
LAN interconnection
Propagation delay
Sun
Timing
Voltage
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Summary:This paper presents a methodology to accurately evaluate the input waveforms of CMOS gates for static timing analysis (STA) in the presence of crosstalk noise. Currently, gate delay is calculated by looking-up 2-dimension table using input waveform slope and gate load capacitance, and CMOS gate input waveforms are usually represented using the latest arrival time and transition time (slope) conventionally. Generally these two parameters are calculated based on time instances at which the input waveform passes through predetermined voltage levels. However, this method can not accurately model the input waveforms with increasing crosstalk noise nowadays. The key contribution of the proposed methodology is to improve the efficiency to approximate the input waveform based on the sensitivity of the output to input waveforms. Experimental results demonstrate higher accuracy of our methodology comparing with the best of the existing techniques.
ISBN:1424425875
9781424425877
ISSN:2324-8475
DOI:10.1109/CAS-ICTD.2009.4960832