An analog SAT solver based on a deterministic dynamical system: (Invited paper)

Boolean Satisfiability (SAT), the first problem proven to be NP-complete, is intractable on digital computers based on the von Neumann architecture. An efficient SAT solver can benefit many applications such as artificial intelligence, circuit design, and functional verification. Recently, a SAT sol...

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Bibliographic Details
Published in2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 794 - 799
Main Authors Xunzhao Yin, Toroczkai, Zoltan, Hu, Xiaobo Sharon
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2017
Subjects
Analog circuits
Computers
Differential equations
Electronic mail
Hardware
Mathematical model
Software
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Summary:Boolean Satisfiability (SAT), the first problem proven to be NP-complete, is intractable on digital computers based on the von Neumann architecture. An efficient SAT solver can benefit many applications such as artificial intelligence, circuit design, and functional verification. Recently, a SAT solver approach based on a deterministic, continuous-time dynamical system (CTDS) was introduced [1]. This approach shows polynomial analog time-complexity on even the hardest k-SAT (k ≥ 3) problem instances, but at an energy cost dependent on exponentially growing auxiliary variables. This paper reports a novel analog hardware SAT solver, AC-SAT, implementing the CTDS via incorporating novel, analog circuit design ideas. AC-SAT is intended to be used as a co-processor and is programmable for handling different problem specifications. Furthermore, with its modular design, AC-SAT can be readily extended to solve larger size problems. SPICE simulation results show that AC-SAT can indeed solve the SAT problems, and it has speedup factors of ~10 4 on even the hardest 3-SAT problems, when compared with a state-of-the-art SAT solver on digital computers.
ISSN:1558-2434
DOI:10.1109/ICCAD.2017.8203858