Characterization of gate overlap capacitances and effective channel size in MOSFETs

Characterization of MOSFET gate overlap capacitances is briefly discussed. A new approach for extraction of the gate overlap capacitances and of the channel width and length variation with respect to the design of the planar MOSFETs is presented and illustrated using experimental data.

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Bibliographic Details
Published in2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) pp. 1 - 4
Main Authors Tomaszewski, Daniel, Gluszko, Grzegorz, Malesmska, Jolanta
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2018
Subjects
Capacitance
Capacitance measurement
Capacitance-voltage characteristics
channel narrowing
channel shortening
CV characteristics
Estimation
Logic gates
MOSFET
overlap capacitances
Size measurement
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Summary:Characterization of MOSFET gate overlap capacitances is briefly discussed. A new approach for extraction of the gate overlap capacitances and of the channel width and length variation with respect to the design of the planar MOSFETs is presented and illustrated using experimental data.
ISSN:2472-9132
DOI:10.1109/ULIS.2018.8354765