Calibrating capacitor mismatch and comparator offset for 1-bit/stage pipelined ADCs

In this paper, we present an efficient calibration technique for 1-bit/stage pipelined analog-to-digital converters (ADCs). The proposed technique calibrates capacitor mismatch and comparator offset induced non-ideal ADC output behavior; it is a two-phase calibration scheme that relies on linear his...

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Bibliographic Details
Published in2008 IEEE 14th International Mixed-Signals, Sensors, and Systems Test Workshop pp. 1 - 6
Main Authors Xuan-Lun Huang, Yuan-Chi Yu, Jiun-Lang Huang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2008
Subjects
Calibration
Capacitors
Gain
Histograms
Pipelines
Registers
Testing
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Summary:In this paper, we present an efficient calibration technique for 1-bit/stage pipelined analog-to-digital converters (ADCs). The proposed technique calibrates capacitor mismatch and comparator offset induced non-ideal ADC output behavior; it is a two-phase calibration scheme that relies on linear histogram testing to collect the required information. In the first phase, it calibrates the missing-decision-level errors by capacitor resizing. Unlike previous works which require large capacitor arrays, only few switches are added to the circuit. The second phase performs missing code elimination. It achieves better calibrated linearity and provides better mismatch tolerance than the traditional digital calibration technique. Simulation results show that the proposed technique effectively improves INL and DNL.
ISBN:9781424423958
1424423953
DOI:10.1109/IMS3TW.2008.4581608