Yield Challenges and Innovative Inspection & Metrology Solutions for Sub-10nm Manufacturing

• Published in: 2019 Electron Devices Technology and Manufacturing Conference (EDTM) pp. 182 - 184
• Main Authors: Chen, Hardy, Lenox, Chet, Saville, Barry
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2019
• Subjects: Defect Inspection; DTCO; EUV; FSAV; Inspection; Manufacturing; Metrology; Monitoring; SAGC; Semiconductor device modeling; Signal to noise ratio; Simulation-guided stack engineering; Ultraviolet sources
• DOI: 10.1109/EDTM.2019.8731251

Computational simulations offer a cost-effective way to peek into future challenges in wafer manufacturing. In this paper, a variety of simulation methods will be discussed, including their ability to better predict process changes and the implications to inspection and metrology. Process simulation software Coventor SEMulator3D ® was used to visualize process variations and an in-house rigorous coupled-wave analysis (RCWA) engine was built to calculate the propagation of E-field through wafer topology [1]. By simulating a self-aligned gate contact and via process, we estimate the process window, defects-of-interest, and metrology requirements. Another study estimates the yield impact of film particles being decorated through different process steps. The final series of work attempts to understand the responses of inspection tools to varied defect and pitch sizes on an extreme ultraviolet lithography (EUV) line and space pattern. As a semiconductor equipment manufacturer, KLA-Tencor values the detail provided by these simulations as they highlight potential yield challenges, which guides our development of next-generation process control solutions [2], [3].