A flexible and fast software implementation of the FFT on the BPE platform

• Published in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 1467 - 1470
• Main Authors: Cupaiuolo, T., Lo Iacono, Daniele
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2012
• Subjects: Clocks; Memory management; Pipelines; SIMD; Software; Software Defined Radio (SDR); software Fast Fourier Transform (FFT); Throughput; vector processors; Vectors; VLIW architectures
• ISBN: 1457721457; 9781457721458
• ISSN: 1530-1591; 1558-1101
• DOI: 10.1109/DATE.2012.6176598

The importance of having an efficient Fast Fourier Transform (FFT) implementation is universally recognized as one of the key enablers for the development of new and more powerful signal processing algorithms. In the field of telecommunications, one of its most recent applications is the Orthogonal Frequency Division Multiplexing (OFDM) modulation technique, whose superiority is recognized and endorsed by several standards. However, the horizon of standards is so wide and heterogeneous that a single FFT implementation hardly satisfies them all. In order to have a reusable, easily extensible and reconfigurable solution, most of the baseband processing is moving towards a software implementation: to this end several new Digital Signal Processor (DSP) architectures are emerging, each with its own set of differentiating properties. Within this context, we propose a software implementation of the FFT on the Block Processing Engine (BPE) platform. Several implementations have been investigated, ranging from a single instruction based approach, to others employing several instructions either in parallel or in pipeline. The outcome is a flexible set of solutions that leaves degrees of freedom in terms of computational load, achievable throughput and power consumption. The proposed implementations closely approach the theoretical clock cycles expected by dedicated hardware counterpart, thus making it a concrete alternative.