A low jitter self-calibration PLL for 10Gbps SoC transmission links application

A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10 Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small KVCO...

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Bibliographic Details
Published in2008 15th IEEE International Conference on Electronics, Circuits and Systems pp. 786 - 789
Main Authors Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2008
Subjects
Clocks
CMOS technology
Jitter
Land surface temperature
Noise reduction
Phase locked loops
Power dissipation
System-on-a-chip
Voltage control
Voltage-controlled oscillators
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Summary:A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10 Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small KVCO can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13 mum CMOS technology. The PLL output jitter is 18.55 ps (p-p) where the reference clock jitter is 20 ps (p-p). The total power dissipation is 21 mW at 2.5-GHz and the core area is 0.08 mm 2 .
ISBN:1424421810
9781424421817
DOI:10.1109/ICECS.2008.4674971