P-type tunneling FET on Si (110) substrate with anisotropic effect

• Published in: 69th Device Research Conference pp. 207 - 208
• Main Authors: Lee, M. H., Kao, C.-Y, Yang, C.-L, Lee, C.-H
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2011
• Subjects: Capacitance-voltage characteristics; Logic gates; Silicon; Substrates; Tin; Tunneling
• ISBN: 9781612842431; 1612842437
• ISSN: 1548-3770; 2640-6853
• DOI: 10.1109/DRC.2011.5994500

The promising potential of tunneling FETs (TFETs) for steep switch behavior with gate controlled band-to-band tunneling (BTBT) mechanism has attracted much attention for supply voltage (V<;sub>;DD<;/sub>;) scaling and power consumption next generation CMOS. However, the challenge for TFETs is lower drive currents as compare with MOSFET due to a high conductance resistance while reverse bias. Tunneling FETs (TFETs) operates with band-to-band tunneling current that change with the channel potential more abruptly than thermionic emission current. In order to obtain high I<;sub>;ON<;/sub>; without sacrificing I<;sub>;OFF<;/sub>;, and the high-k dielectric and metal gate are integrated as gate stack. To obtain high quality and avoid crystallizing of high-K layer, the gate last process was performed in this work. For N-TFET, much works have been reported on the SS improvement. For P-TFET, Bhuwalka et al. reported the ambipolar working of vertical TFET with negative gate bias, which obtain SS <; 60mV/dec. In this work, we will demonstrate HK/MG (high-K/metal gate) P-TFET with the gate last process, and discuss the anisotropic effect on (110) substrate.Anisotropic Effect