Low-power test planning for arbitrary at-speed delay-test clock schemes

High delay-fault coverage requires rather sophisticated clocking schemes in test mode, which usually combine launch-on-shift and launch-on-capture strategies. These complex clocking schemes make low power test planning more difficult as initialization, justification and propagation require multiple...

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Bibliographic Details
Published in2010 28th VLSI Test Symposium (VTS) pp. 93 - 98
Main Authors Zoellin, Christian G, Wunderlich, Hans-Joachim
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2010
Subjects
Automatic testing
Built-in self-test
Circuit faults
Circuit testing
Clocks
Combinational circuits
Delay
Delay test
Electrical fault detection
Energy consumption
Fault detection
power-aware testing
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ISBN9781424466498
1424466490
ISSN1093-0167
DOI10.1109/VTS.2010.5469607

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Summary:High delay-fault coverage requires rather sophisticated clocking schemes in test mode, which usually combine launch-on-shift and launch-on-capture strategies. These complex clocking schemes make low power test planning more difficult as initialization, justification and propagation require multiple clock cycles. This paper describes a unified method to map the sequential test planning problem to a combinational circuit representation. The combinational representation is subject to known algorithms for efficient low power built-in self-test planning. Experimental results for a set of industrial circuits show that even rather complex test clocking schemes lead to an efficient low power test plan.
ISBN:9781424466498
1424466490
ISSN:1093-0167
DOI:10.1109/VTS.2010.5469607