Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two s...
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Published in | 2009 IEEE International Electron Devices Meeting (IEDM) pp. 1 - 4 |
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Main Authors | , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.12.2009
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Subjects | |
Online Access | Get full text |
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Summary: | We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 ¿A/¿m, respectively, at I off = 300 pA/¿m, V DD = 0.9V, and L G = 25 nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low V T variability is achieved with A Vt of 1.25 mV·¿m in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics. |
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ISBN: | 9781424456390 1424456398 |
ISSN: | 0163-1918 2156-017X |
DOI: | 10.1109/IEDM.2009.5424422 |