Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors

• Published in: 2009 Asia and South Pacific Design Automation Conference pp. 449 - 454
• Main Authors: Taniguchi, I., Jayapala, M., Raghavan, P., Catthoor, F., Sakanushi, K., Takeuchi, Y., Imai, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2009
• Subjects: Arithmetic; Computer architecture; Embedded system; Energy consumption; Extraterrestrial measurements; Image processing; Reconfigurable architectures; Space technology; Table lookup; VLIW
• ISBN: 9781424427482; 1424427487
• ISSN: 2153-6961; 2153-697X
• DOI: 10.1109/ASPDAC.2009.4796521

Systematic architecture exploration from vast solution space is a complex problem in embedded system design. It is very difficult to explore a best architecture fast and accurately because accurate evaluation usually consumes significant amount of time for point in the solution space. In this paper, we propose fast and systematic architecture exploration method for address generation unit (AGU) based on a coarse grained reconfigurable architecture model. First we prove that a set of Pareto solutions of cycle vs energy becomes a subset of Pareto solutions of cycle vs area under some practical assumptions. In addition we propose ldquoOptimistic cycle (OC)rdquo metric to find out promising solutions from vast solution space. Based on this metric we also propose a fast architecture exploration algorithm which only applies mapping to promising architectures. Using the proposed systematic architecture exploration method, we show that we can obtain almost the same trade-off points as the exhaustive search method and also that our method is about 164 times faster than exhaustive search.