RTL property abstraction for TLM assertion-based verification
Different techniques and commercial tools are at the state of the art to reuse existing RTL IP implementations to generate more abstract (i.e., TLM) IP models for systemlevel design. In contrast, reusing, at TLM, an assertion-based verification (ABV) environment originally developed for an RTL IP is...
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Published in | 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 85 - 90 |
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Main Authors | , , , |
Format | Conference Proceeding |
Language | English |
Published |
EDAA
01.03.2015
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Subjects | |
Online Access | Get full text |
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Summary: | Different techniques and commercial tools are at the state of the art to reuse existing RTL IP implementations to generate more abstract (i.e., TLM) IP models for systemlevel design. In contrast, reusing, at TLM, an assertion-based verification (ABV) environment originally developed for an RTL IP is still an open problem. The lack of an effective and efficient solution forces verification engineers to shoulder a time consuming and error-prone manual re-definition, at TLM, of existing assertion libraries. This paper is intended to fill in the gap by presenting a technique to automatically abstract properties defined for RTL IPs with the aim of creating dynamic ABV environments for the corresponding TLM models. |
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ISSN: | 1530-1591 1558-1101 |
DOI: | 10.7873/DATE.2015.0121 |