An integrated patch-clamp amplifier for ultra-low current measurement on solid-state nanopore

In this paper, an integrated low-noise patch-clamp amplifier for a solid-state nanopore application is proposed which is composed of three stages: 1) a trans-impedance amplifier (TIA), 2) a voltage-gain amplifier (VGA), and 3) a unity-gain buffer. Because the first stage amplifier makes dominant imp...

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Bibliographic Details
Published in2010 International SoC Design Conference pp. 424 - 427
Main Authors Kim, Jungsuk, Wang, Gang, Dunbar, W.B., Pedrotti, Kenneth
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2010
Subjects
Bandwidth
CMOS integrated circuits
DNA
Gain
Nanobioscience
Noise
Radio frequency
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Summary:In this paper, an integrated low-noise patch-clamp amplifier for a solid-state nanopore application is proposed which is composed of three stages: 1) a trans-impedance amplifier (TIA), 2) a voltage-gain amplifier (VGA), and 3) a unity-gain buffer. Because the first stage amplifier makes dominant impacts on gain, bandwidth, noise, stability, and area of the patch-clamp amplifier, in this work, we present the design analysis for the TIA and its optimal feedback resistance. The proposed patch-clamp amplifier has a maximum gain of 152.2dBΩ, an input-referred noise of 11.3pA RMS within bandwidth of 10 KHz, and occupies an active die-area of 0.0625mm 2 . This amplifier is under fabrication in a 0.35μm CMOS 4M2P Process.
ISBN:1424486335
9781424486335
DOI:10.1109/SOCDC.2010.5682879