Dual-mode 10MHz BW 4.8/6.3mW reconfigurable lowpass/complex bandpass CT ΣΔ modulator with 65.8/74.2dB DR for a zero/low-IF SDR receiver

• Published in: 2014 IEEE Radio Frequency Integrated Circuits Symposium pp. 313 - 316
• Main Authors: Yang Xu, Zehong Zhang, Baoyong Chi, Qiongbing Liu, Xinwang Zhang, Zhihua Wang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2014
• Subjects: CMOS integrated circuits; complex bandpass; Continuous-time (CT); Filtering theory; Logic gates; lowpass; Modulation; Receivers; reconfigurable; Resistors; sigma-delta (ΣΔ) modulator; Switches
• ISBN: 1479938629; 9781479938629
• ISSN: 1529-2517; 2375-0995
• DOI: 10.1109/RFIC.2014.6851729

A dual-mode wideband reconfigurable lowpass /complex bandpass continuous-time sigma-delta (LP/CBP CT ΣΔ) modulator with digitally-assisting integrated in a zero/ low-IF SDR receiver is presented. The proposed modulator is capable of switching in either 3 rd -order LP or 2 nd -order CBP with 10MHz bandwidth (BW) in each mode. The power-efficient amplifiers in active-RC integrators are implemented with active feedforward and anti-pole-splitting compensation schemes. The 2-bit digitally-switched current-steering DAC with gate-leakage compensation is proposed to cover the current variation in LP/CBP mode and solve the unavoidable gate-leakage issue in deep submicron CMOS. Fabricated in 65nm CMOS, the modulator achieves 65.8dB DR, 62.2dB peak SNDR in LP 10MHz BW mode and 74.2dB DR, 63.9dB SNDR across 10MHz signal-band with center frequency of 6MHz in CBP mode, occupying a core area of 0.39mm 2 . Powered by a 1.2-V supply, the effective power consumption is only 4.8 and 6.3mW in LP and CBP mode respectively, resulting in measured FoMs of 0.23 and 0.25pJ/conversion.