Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA)

The non-volatile field programmable gate array (FPGA) is a promising candidate for the ultra-low-power computing due to its flexibility. However, the non-volatile devices have a critical drawback of reliability due to the process variations in read operation. We propose a novel look-up table scheme...

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Bibliographic Details
Published in2016 International SoC Design Conference (ISOCC) pp. 101 - 102
Main Authors Kangwook Jo, Kyungseon Cho, Hongil Yoon
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2016
Subjects
Clocks
Field programmable gate arrays
Logic gates
look-up table
Magnetic tunneling
Non-volatile FPGA
Random access memory
STT-MRAM
Table lookup
Transistors
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Summary:The non-volatile field programmable gate array (FPGA) is a promising candidate for the ultra-low-power computing due to its flexibility. However, the non-volatile devices have a critical drawback of reliability due to the process variations in read operation. We propose a novel look-up table scheme using the spin-torque transfer magnetic RAM with high variation tolerance and low power consumption. The proposed 8-input look-up table (LUT) has a 74.4% smaller read power consumption than that of the conventional 8-input SRAM-based LUT. The area of the proposed LUT is comparable to that of the conventional SRAM-based LUT.
DOI:10.1109/ISOCC.2016.7799753