A 50 MHz-6 GHz, 2 × 2 MIMO, reconfigurable architecture, software-defined radio in 130nm CMOS

A monolithic 50 MHz-6 GHz software-defined radio transceiver with two transmit (TX) and two receive (RX) channels to support 2 × 2 MIMO is implemented in 130nm CMOS. The transmitter's and receiver's frequency translation modes are reconfigurable to direct conversion or dual up-down convers...

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Bibliographic Details
Published in2014 IEEE Radio Frequency Integrated Circuits Symposium pp. 329 - 332
Main Authors Analui, Behnam, Mercer, Timothy, Mandegaran, Sam, Goel, Ankush, Hashemi, Hossein
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2014
Subjects
CMOS
Current measurement
Frequency conversion
Frequency synthesizers
MIMO
Noise
Radio transmitters
Receivers
Reconfigurable
SDR
Transceiver
Transceivers
Wideband
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Summary:A monolithic 50 MHz-6 GHz software-defined radio transceiver with two transmit (TX) and two receive (RX) channels to support 2 × 2 MIMO is implemented in 130nm CMOS. The transmitter's and receiver's frequency translation modes are reconfigurable to direct conversion or dual up-down conversion, featuring an on chip Q-enhanced 3 GHz 6-pole Chebyshev IF BPF in the dual conversion mode. The chip also includes two independent integrated wide-band frequency synthesizers for TX and RX paths to support Frequency Division Duplex (FDD) radios. Each frequency synthesizer has an integrated 50 MHz Direct Digital Synthesis (DDS) based reference into an integer-N PLL with integrated 3-tank VCOs, integrated loop-filter, and a zero-spur phase-frequency detector, to achieve low-spur and high resolution, simultaneously. The radio has >0 dBm TXP -1dB and >70 dB RX blocker tolerance (in-band and out of band) with <; 900 mW worst case total power consumption per transceiver channel.
ISBN:1479938629
9781479938629
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2014.6851733