Synthesis of self-resetting stage logic pipelines

In this paper, a methodology to synthesize SRSL pipelines has been presented. The synthesis of SRSL pipelines is formulated as an integer programming (IP) problem subject to area and timing constraints for which an exact procedure is proposed. Currently, the proposed solution is being implemented an...

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Bibliographic Details
Published inIEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) pp. 260 - 262
Main Authors Abdelhalim Alsharqawi, Abdel Ejnioui
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
Circuit synthesis
Clocks
Costs
Delay
Design methodology
Gravity
Logic
Network synthesis
Pipeline processing
Switches
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Summary:In this paper, a methodology to synthesize SRSL pipelines has been presented. The synthesis of SRSL pipelines is formulated as an integer programming (IP) problem subject to area and timing constraints for which an exact procedure is proposed. Currently, the proposed solution is being implemented and tested on a set of benchmark circuits. Also, fast heuristics are being developed to synthesize large gate netlists into SRSL pipelines.
ISBN:076952365X
9780769523651
ISSN:2159-3469
DOI:10.1109/ISVLSI.2005.70