Architectural evaluation of 3D stacked RRAM caches

• Published in: 2009 IEEE International Conference on 3D System Integration pp. 1 - 4
• Main Authors: Lewis, D.L., Lee, H.-H.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2009
• Subjects: Capacitors; Circuits; Electric resistance; Logic devices; Memristors; Nonvolatile memory; Random access memory; Resistors; Silicon; Voltage
• ISBN: 9781424445110; 1424445116
• DOI: 10.1109/3DIC.2009.5306582

The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resistance changes as current passes through it, giving the device a memory of the past system state. The immediately obvious application of such a device is in a non-volatile memory, wherein high- and low-resistance states are used to store binary values. A memory array of memristors forms what is called a resistive RAM or RRAM. In this paper, we survey the memristors that have been produced by a number of different research teams and present a point-by-point comparison between DRAM and this new RRAM, based on both existent and expected near-term memristor devices. In particular, we consider the case of a die-stacked 3D memory that is integrated onto a logic die and evaluate which memory is best suited for the job. While still suffering a few shortcomings, RRAM proves itself a very interesting design alternative to well-established DRAM technologies.