Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor

We developed a Wide IO DRAM controller chip with Through Silicon Via (TSV) technology. Test circuitry is embedded in the micro-IOs placed between the fine pitch TSVs which can reject TSV connectivity failures prior to stacking process. In order to reduce Vmin degradation induced by 512 DQs simultane...

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Bibliographic Details
Published inProceedings of the IEEE 2013 Custom Integrated Circuits Conference pp. 1 - 4
Main Authors Nomura, Takao, Mori, Ryo, Ito, Munehiro, Takayanagi, Koji, Ochiai, Toshihiko, Fukuoka, Kazuki, Otsuga, Kazuo, Nii, Koji, Morita, Sadayuki, Hashimoto, Tomoaki, Kida, Tsuyoshi, Yamada, Junichi, Tanaka, Hideki
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2013
Subjects
Capacitance
fully digital noise monitor
Impedance
impedance optimization
Monitoring
Noise
Optimization
pre-bonding test
Random access memory
simultaneous switching noise
Through-silicon vias
TSV
Wide IO DRAM
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Summary:We developed a Wide IO DRAM controller chip with Through Silicon Via (TSV) technology. Test circuitry is embedded in the micro-IOs placed between the fine pitch TSVs which can reject TSV connectivity failures prior to stacking process. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance optimization method utilizing a full digital noise monitor. We achieved 12.8 GB/s operation, while IO power was reduced by 89 % compared to LPDDR3.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2013.6658415