A novel VLSI architecture for Walsh-Hadamard transform

• Published in: 2nd Asia Symposium on Quality Electronic Design (ASQED) pp. 146 - 150
• Main Authors: Ghosh, S, Talapatra, S, Maity, S P, Rahaman, H
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2010
• Subjects: Clocks; Discrete transforms; Energy consumption; Energy efficiency; Field programmable gate arrays; FPGA; Hardware; HVMA; Merging; Signal processing algorithms; Throughput; Very large scale integration; VLSI; Walsh-Hadamard Transform
• ISBN: 9781424478095; 142447809X
• DOI: 10.1109/ASQED.2010.5548230

In this paper, a novel VLSI architecture for one dimensional Walsh-Hadamard transform (WHT) is proposed. The core of the architecture is the HVMA (Hadamard Vector Merging Adder) that adds the products of input data words and transform (Hadamard) matrix elements in parallel using a (4:2) compressor based carry-save tree structure. The core also exploits the Hadamard matrix's property of equal distribution of +1 and -1 in all rows and columns, except for the first row and the first column. The VLSI implementation of the architecture for transforming an (8×8) image block using Field Programmable Gate Array (FPGA) results in clock frequency of 101 MHz, and power consumption of 424 mW. The energy consumption, calculated as power-latency product, is 678.4 nJ, which is 20.6% lower than the existing architecture with the minimum value reported in the literature. The throughput for a (8×8) block is 633.66ns which is 46.9% lower than the fastest architecture.