Robustness Analysis of Different AES Implementations on SRAM Based FPGAs

Common features for comparing AES implementations are the latency and throughput of the module as well as its resource requirements. This work evaluates the robustness against punctual errors in the FPGA caused by SEUs or other effects for a variety of AES implementations in order to provide a possi...

Full description

Saved in:
Bibliographic Details
Published in2011 International Conference on Reconfigurable Computing and FPGAs pp. 255 - 260
Main Authors Kretzschmar, U., Astarloa, A., Lazaro, J., Bidarte, U., Jimenez, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2011
Subjects
AES
Encryption
Field programmable gate arrays
FPGA
Hardware
Microcontrollers
Robustness
robustness analysis
SEU injection
Software
Throughput
Online AccessGet full text

Cover

More Information
Summary:Common features for comparing AES implementations are the latency and throughput of the module as well as its resource requirements. This work evaluates the robustness against punctual errors in the FPGA caused by SEUs or other effects for a variety of AES implementations in order to provide a possible additional feature differentiating various architectures. The AES implementations included in this work span from a speed of more than one Mcycle for one encryption to 16 cycles per encryption. A fault injection flow is executed on the different implementations in order to determine their robustness against these punctual errors.
ISBN:9781457717345
1457717344
ISSN:2325-6532
2640-0472
DOI:10.1109/ReConFig.2011.80