Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA

An efficient architecture for implementation of double precision floating point multiplication on field programmable gate array (FPGA) is presented, based on the use of partial block multipliers. The proposed module gives excellent performance with efficient use of resources, achieving upto 292 MHz...

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Bibliographic Details
Published in2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems pp. 1 - 4
Main Authors Jaiswal, M.K., Chandrachoodan, N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2008
Subjects
Costs
Delay
Double precision
Field programmable gate arrays
Floating point multiplication
Floating-point arithmetic
FPGA
Hardware
Libraries
Logic
Partial block multiplier
Region 10
Sections
Signal processing
Virtex
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Summary:An efficient architecture for implementation of double precision floating point multiplication on field programmable gate array (FPGA) is presented, based on the use of partial block multipliers. The proposed module gives excellent performance with efficient use of resources, achieving upto 292 MHz on a Xilinx Virtex II Pro device and 325 MHz on a Xilinx Virtex IV. The cost of the design is an error when compared to the IEEE standard, of up to 1 unit in last place (ulp) when used with partial nearest value rounding, or up to 2 ulp without rounding. Comparisons against the best reported multipliers in the literature show that the proposed module can outperform them.
ISSN:2164-7011
2690-3423
DOI:10.1109/ICIINFS.2008.4798393